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ttl 死循环
:BL1:9ac50e:bb16dc;FEAT:BDFC31BC:0 OC:3;RCY:0;EMMC:0;READ:0;0.0;0.0;CHK:0;
TE: 239034
BL2 Built : 11:58:42, May 27 2017.
gxl gc3c9a84 - xiaobo.gu@droid05
set vdd cpu_a to 1120 mv
set vdd cpu_b to 1050 mv
set vddee to 1000 mv
Board ID = 4
CPU clk: 1200MHz
DQS-corr enabled
DDR scramble enabled
DDR3 chl: Rank0+1 @ 912MHz - FAIL
DDR3 chl: Rank0 @ 912MHz - FAIL
DDR3 chl: Rank0 16bit @ 912MHz - FAIL
DDR4 chl: Rank0+1 @ 1008MHzGXL:BL1:9ac50e:bb16dc;FEAT:BDFC31BC:0 OC:3;RCY:0;EMMC:0;READ:0;0.0;0.0;CHK:0;
TE: 237436
BL2 Built : 11:58:42, May 27 2017.
gxl gc3c9a84 - xiaobo.gu@droid05
set vdd cpu_a to 1120 mv
set vdd cpu_b to 1050 mv
set vddee to 1000 mv
Board ID = 4
CPU clk: 1200MHz
DQS-corr enabled
DDR scramble enabled
DDR3 chl: Rank0+1 @ 912MHz - FAIL
DDR3 chl: Rank0 @ 912MHz - FAIL
DDR3 chl: Rank0 16bit @ 912MHz - FAIL
DDR4 chl: Rank0+1 @ 1008MHz
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